Release Note for BCM5714 Family BOOT Code Firmware
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5714, 5714s, 5715, 5715s, 5780, 5780s
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Version 3.28 -- 07/25/06
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1. Wrong revision.
Problem: (CQ26037)
The chip revision posted in Shared memory 0xd2c was incorrect.
Cause:
Bug introduced in version 3.26. The metal revision mask was changed
by other project incorrectly.
Fix:
Changed back to the correct mask.
Impact:
Any revision sensitive routines or workaround was affected by this.
One example is IPMI firmware: when IPMI is enabled, the firmware
will based on wrong revision to initialize GPhy incorrectly. As
result, the link disappears.
2. Changed VPD default Product String
Enhancement:
Based on MRD, for Fiber device, the VPD default product string is
changed from "Broadcom NetXtreme Gigabit Ethernet Controller" to
"Broadcom NetXtreme Gigabit Fiber Controller"
Impact:
Any application uses product string based on VPD data, the
string will be changed. This change only affect fiber devices.
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Version 3.27 -- 06/05/06
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1. The minor version number is not correct
Problem:
The minor version number on the version 3.26 will show 25 which should be 26.
Cause:
Version number not updated correctly.
Fix:
Update the minor version number to 27.
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Version 3.26 -- 06/01/06
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1. Linux driver cannot write NVRAM properly for STM45PE10 flash
Problem: CQ#25116
Linux driver cannot program the NVRAM if the flash is STM45PE10.
Cause:
BCM5714 family is support ST25 not ST45 by default, so the bootcode need
to drop the correct value for the NVRAM config3 register if is ST45 flash.
Fix:
For BCM5714 family chips if the flash is ST45 set the correct value to config3.
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Version 3.25 -- 3/28/06
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1. Keep power up if only one port was disabled for 5780s.
Problem: CQ#23930A
If power down one port of 5780s, will cause the other port was powered down
too.
Cause:
This is the same issue as CQ12944.
In Hamilton or HT-LE serdes devices, when shutting down phy by setting
bit 11 of MDIO register 0 (Command register) will shutdown both port's phy.
Fix:
Do not power down 5780s if the other port is enabled.
Impact:
Since the original code had workaround applied to HTLE A4 or older chip already,
this change will only affect B0 or newer chip. This version will apply the
workaround for all HTLE revision chips. No impact to Hamilton devices.
2. Keep the disabled port alive.
Problem: CQ#23969
Customer request that if management firmware (UMP) is enabled on a particular
port, when they disable the LAN (host) functionality of that same port, the UMP
still functional.
Cause:
Bootcode does not load any management firmware if that port has been disabled.
Fix:
Modify bootcode to check if Management firmware is present and enabled for
the disabled port. If management is enabled, bootcode will load management
firmware and keep that part functional.
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Version 3.24 -- 2/1/06
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1. enabled ECD 14583
Problem:
The change in version 3.23, #1, was not programming correctly.
Cause:
Coding error
Fix:
Fixed the code
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Version 3.23 -- 2/1/06
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1. Enabled ECD 14583
Enhancement: CQ#14583,14489,13719,14359,14360
Enabled ASIC fix for ECD 14583. Without enabling the fix, CPU is having
problem accessing invalid address.
2. Changed revision reading method
Enhancement:
The code is changed to read revision from register 0x2018 when revision
id (PCI config. space 0x8) is not zero. This is done regardless of power
state.
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Version 3.22 -- 1/12/06
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1. Enabled ECD 13216
Enhancement:
The ECD13216 was disabled in v3.19. Now, we found out that extra step
(enabling signal detect) needed to take place for the fix to be working.
Thus, enabled back ECD 13216.
2. Move GPIO initialization to Phase1 code
Enhancement:
Originally, activating VAUX power was done in phase 2 bootcode.
However, once driver waited for phase1 signature, driver may start to
configure GPIO for WoL setting. The 2nd phase GPIO initialization may
destroy driver's setting.
This problem was worked around by driver by waiting for phase2 bootcode
to be loaded before the GPIO initialization. This change does not
affect anything since driver already have the work around.
3. Increased Link checking period for VAux only state
Enhancement:
Currently, the link check is done in about every 1 second when VMain
present. When bootcode is running under VAux only state, the core clock
is much slower. This cause link check period too long. Added a logic that
both state can poll link status at around 1 second period.
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Version 3.21 -- 10/7/05
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1. Changed Algorithm for the change in version 3.18 #1
Problem:
When device change from forced mode to Automode, even though physically
shows link, it cannot pass the traffic.
Cause:
After the remote partner switch to Automode, our device will stay in
forced mode.
Fix:
Changed the algorithm.
impact:
Only affect fiber devices.
2. Added GPIO control in the configuration
Enhancement: CQ#14224
Added new defines for GPIO0 and GPIO2 pins. Each pin can be set to input
or output pin. When set to output, the value also can be defined.
To set the configuration, b57diag V8.28 or newer is required.
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Version 3.20 -- 9/19/05
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1. Fixed CQ#13517
Problem: CQ#13517
The symptom for CQ#13517 showed up again in version 3.19.
(Inconsistent results enabling/disabling interfaces on Hamiton/Montera/HT)
Cause:
When added a logic in version 3.19 to detect the 5714/15-A2/5780-B0 or
newer revision in VAUX only state, the bug was introduced. Bootcode was
not able to determine correct version number for 5714/15 A1/ 5780 A4 or
older revisions. Because of this, it shuts down the PHY when WoL is
disabled and caused other port to shutdown also. (ASIC bug CQ#12944)
Fix:
Fixed the software bug.
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Version 3.19 -- 9/12/05
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1. Removed workaround ECD 13216
Problem: CQ#13942, CQ#13949
After connecting the cable to switch, the switch side shows link but
the device side does not show link.
Cause:
The ECD 13216 did not work correctly. After turning on this ASIC bug
fix, the LED does not get turned.
Fix:
Disabled ECD 13216 ASIC fix.
Note:
This change only affect Hamilton A2/HTLE B0 or later devices.
2. Changed VAUX only state Revision check
Problem:
When there is no VMain, firmware could not tell the revision.
Cause:
PCI config. register are not accessible when there is VMain and the
revision register is in PCI config. domain.
Fix:
Read register 0x6000 reset default value. If bit 1 is set, this is
Hamilton A2 or HTLE B0 or newer.
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Version 3.18 -- 9/9/05
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1. Added logic to workaround CQ#13878
Problem: CQ#13878
Link cannot be established before loading driver.
Cause:
By default, the hardware is in Autonegotiation mode. If the link
partner is not auto-negotiation capable, the link could not be
established.
Fix:
Put a logic to check for the link status. When link is not up, it
will alter the mode between auto mode and forced 1000F mode.
This logic is activated only if not driver reset and there is no link.
2. Fixed CQ#13922 and CQ#13924
Problem:
When WoL is disabled in NVRAM, OOB or DOS shutdown will cause the remote
link partner to link at speed 10 in copper HTLE devices.
Cause:
In bootcode version 3.16, the code has been changed to apply port work
around based on revision. When there is no VMain, the revision register
was not readable. It always returns 0 (A0). So, the work around for port
shutdown (CQ#13517) was applied. When port is not shutdown but put in
power saving mode, the link still have energy and the link partner can
detect the link speed 10.
Fix:
Changed to code to not to apply the work around for all copper devices.
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Version 3.17 -- 9/8/05
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1. Enabled "slow latency Mbuf access"
Problem:
There was a problem when internal CPU accessing to the RxMbuf.
Cause:
LSI team found there is a timing violation between the internal CPU
accessing to the RxMbuf, and the only way to workaround this is to
set the 0x4000[28] which is to enable the "slow latency Mbuf access"
from the internal CPU.
Fix:
Enabled "slow latency Mbuf access"
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Version 3.16 -- 9/7/05
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1. Fixed the workaround in version 3.12, #2.
Problem: CQ#13517
When disabling only one port, the other port was also get disabled.
Cause:
This problem was initially worked around in version 3.12, #2. But, the
work around was only applied when WoL is enabled in one of the ports.
This symptom showed when WoL was disabled in both ports.
Fix:
Changed the code to apply the workaround without checking WoL status.
2. Not to apply version 3.12, #2, work around for newer devices.
Enhancement:
The newer devices (5714/15 A2, 5780 B0 or newer) has fixed the phy
shutdown issue in ASIC. Therefore, the firmware is changed to apply
the work around (v3.12, #2 or v3.16, #1) only for older revision that
doesn't have ASIC fix. By shutting down the phy completely can save
more power.
Since in VAUX only mode, the firmware cannot determine the chip revision
number, therefore the work around would be unconditionally applied.
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Version 3.15 -- 8/22/05
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1. Enabled ECD 13216 for SERDES devices
Enhancement:
Enable ASIC workaround for ECD 13216.
Synopsis of Bug: Possible LINK displayed when Fibre cable is removed.
A problem with the SERDES/PHY where crosstalk can produce a valid LINK
signal even when there is no Fibre cable present.
Note:
This fix is only available on Hamilton A2/HTLE B0 or newer devices
This change is only for SERDES devices.
2. Enabled ECD 13332
Enhancement:
Changed GRC timeout counter from 64k to 16k cycles.
Note:
This fix is only available on Hamilton A2/HTLE B0 or newer devices
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Version 3.14 -- 8/18/05
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1. Not to override RID if there is hardware default
Problem:
For A2 or newer revision silicon has a hardwired revision value in offset 0x8.
The current bootcode was overriding the value with other value.
Cause:
The register 0x68 was still hardwired as A1. As result, bootcode was updating
0x8 with A1 revision value.
Fix:
Now the bootcode reads offset 0x8, RID first. If the value is a non-zero, bootcode
will not modify the value.
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Version 3.13 -- 6/3/05
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1. Advertise both 1000 fullduplex and 1000 halfduplex for serdes device
Problem: CQ12333
The hardware default for serdes is 1000 fullduplex only. For some switches,
such as Dell PowerConnect 5224 will can only advertise 1000 halfduplex. As
result, the link cannot be established.
Cause:
Third party issue.
Fix:
Advertise both 1000 fullduplex and 1000 halfduplex.
Notes:
This change only affects serdes devices.
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Version 3.12 -- 5/18/05
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1. Fixed shutdown problem in NIC
Problem:
When VMain is turned off, the device loses link (power) when the other port
has WoL/ASF/IPMI disabled.
Cause:
The on-board power cut off circuit can be turned off by either port. The
power should be turned off only if both ports are disabled or no longer needed.
The current code was turning off the power when only one port is shutting down
and cause the other port to lose power.
Fix:
Check other port's configuration and make sure it does turn off power for
the device if one of the port is still active.
Impact:
For LOM, since the shutdown does not use on-board circuit; therefore, it
has no effect.
2. Fixed shutdown problem in Serdes
Problem:
For Serdes, shutting down phy in one port will shutdown phy in other port.
Cause:
Presumed this is a hardware problem. Still under investigation.
Fix:
Changed the code to shutdown Serdes phy only when both phy needs to be
shutdown in both port. For the port not shutting down, to save power,
the phy is placed in super isolate mode.
Impact:
This change only affect serdes devices.
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Version 3.11 -- 5/10/05
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1. Added a new field, Smbus address, in shared memory
Enhancement:
IPMI needed multiple SmBus addresses. The NVRAM address is stored
at NVRAM. This version of bootcode reads the data and store the addresses
in the shared memory 0xd54.
2. Enable Msi upon reset
Problem:
MSI was not working. MSI must be enabled before PCI configuration space's
MSI's bits are functional.
Cause:
MSI was not eanbled by hardware default
Fix:
Enable MSI by bootcode.
3. Removed shutdown bit access
Problem:
When bootcode sets this bit causing system to hang
Cause:
ASIC has an problem when using shutdown bit to shutdown the device
and there is no plan to fix this in ASIC.
Fix:
To workaround this issue, bootcode will not shutdown the device by
shutdown bit, instead powering down each block individually to
conserve power.
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Version 3.10 -- 4/25/05
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1. Branch out bootcode 5780/5780s
Enhancement:
HT-LE bootcodes have been branch out from 5714/5714s.
The new device will be 5780/5780s.
There is no functional change from version 3.09.
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Version 3.09 -- 2/28/05
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1. Post phy id for Serdes device
Problem:
The phy id was not posted for Serdes device.
Cause:
Traditionally, there was no phy id in Serdes device, therefore, the
code was not posting phy id in shared memory for Serdes.
Starting 5714/15, the Serdes device have phy id. Driver needs to rely
on this information when ASF/IPMI is enable. (If ASF/IPMI is enabled
driver cannot access MII registers to read id)
Fix:
Bootcode now read phy id for serdes and post the id to shared memory.
Notes:
This change only affect Serdes devices.
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Version 3.08 -- 2/26/05
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1. Enabled double Ack bug ASIC fix (CQ9987)
Problem:
The ASIC double-ack bug fixed in hardware was not enabled
Cause:
In Shasta project, the double ack bug was worked around with firmware
and did not need to enable ASIC fix; hence, it was not enabled. Since
5714/5 does not have ASIC that do not have this fix, the ASIC fix should
be enabled instead of using software workaround.
Fix:
Enabled the ASIC fix.
2. Fixed the bug in v3.07
Problem:
Revision information was not posted correctly in hwinfo_0, shared memory
0xd2c [0:7].
Cause:
This bug was created in v3.07. Code was erroneously coded.
Fix:
Fixed the software bug.
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Version 3.07 -- 2/17/05
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1. Fixed Link detect problem in HT-LE
Problem:
Link could not be detected for HT-LE serdes device.
Cause:
Hardware problem in HT-LE serdes devices.
Fix:
For HT-LE serdes devices, bit 5 of SerdesTxControl register
needs to be changed in clock edge select.
2. Shared memory version changed to 3.
Enhancement:
hwinfo, (0xd2c), bit 15:8 supports HT-LE.
Bit 9 will be set to indicate this is HT-LE device.
Notes:
HT-LE and 5714 shares same bootcode.
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Version 3.06 -- 2/8/05
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1. Fixed device detection problem
Problem:
The change in 3.05 has limitation that CPU cannot detect the id
in VAUX only state.
Cause:
The Id is located in PCI config. space. When there is no VMain,
there is no PCI clock; thus, the register is not accessible.
Fix:
Changed to use UMP id bit 27 in 6808.
2. Fixed Serdes link problem (For serdes bootcode only)
Problem:
Link would not come up.
Cause:
ASIC had clock edge reversed by default.
Fix:
1. Changed the clock edge
2. MAC needs to be in GMII mode instead of TBI mode.
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Version 3.05 -- 2/2/05
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1. Fixed device detection problem
Problem:
Both device was reporting as primary device
Cause:
ASIC had a bug that reporting both port as primary device
in Misc. Config. Register. (bit 22 of register 0x6804)
Fix:
Changed to read from bit 2, register 0xb8.
Note:
This change will undo the fix in version 3.04, item #1.
By doing so, device detection will not work under VAUX only state.
The fix in v3.04, item#1 will be put back when ASIC has fixed the
device bit in Misc. Config. Register.
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Version 3.04 -- 1/24/05
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1. Fixed VAUX only case Secondary device detection bug
Problem:
The primary or secondary device detection was not working on VAUX only case.
Cause:
PCI config. space was not accessible if there is no VMain
Fix:
Changed the code to always read from Misc. Config. Register.
2. Initialized TxMbuf
Problem:
TxMbuf unused bits were not initialized by ASIC. When some bits are not
initialized, the TxMbuf will not work.
Fix:
Bootcode to initialize the first word of each mbuf cluster in all Txmbuf
range (0x8000-0xd800).
Note:
This change is required for ASF/IPMI to work.
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Version 3.03 (12/14/04)
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1. Applied CPU instruction problem workaround
Problem:
Rev A0 has CPU instruction problem that when CPU reads ASIC registers,
the data could not be used in next instruction.
Cause:
ASIC Bug due to the pipe line.
Workaround:
Replaced all register read instruction with subroutine call to avoid
immidiate use after read.
With this change, bootcode was able to boot properly for some devices.
Once bootcode was able to run correcly, VPD service was able to perform
correctly.
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Version 3.02 (11/17/04)
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1. Fixed Serdes Link problem
Problem:
Cannot detect Link properly
Cause:
There is a bug in HLTE A0 part that both Serdes ports will not get link
unless bit 8 of 0xb50 of CHANNEL 0 is set to 1.
Fix:
Setting "clock edge select", bit 8 at register 0x5b0 (Serdes Rx Ctrl Reg)
Note:
This change is for Serdes (5714s) only.
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Version 3.01 (11/9/04)
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1. Removed PCIE register access
Problem:
5714/5714s do not have PCIE registers. Accessing those registers
can cause CPU to stall.
Fix:
Removed all PCIE register access.
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Version 3.00 (11/9/04)
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Initial Release